The PCB design capabilities of Lepos are as follows: Maximum designed layers: 22 layers Maximum PIN count: 48963 Minimum via: 8 MIL (4 Mil laser hole) Minimum line width: 2.4 MIL Minimum line spacing: 4 MIL Maximum BGA count in a single PCB: 44 Minimum BGA PIN pitch: 0.4 mm Highest speed signal: 10G CML differential signals. Shortest lead time: 6 days for SI, placement, routing for 20000 pin PCB.
